In the absolute maximum ratings of ADuC7061/ADuC7061 (Rev. C) it is stated that digital I/O voltage to DGND is -0.3 V to +3.3 V. If it is intended to interface ADuC706x I/O pins to a 3.3-V system then voltage which occurs on its inputs/outputs may exceed 3.3 V because voltage regulator on the 3.3V site may have a spread of 3.3 V +-5% or even 3.3 V +-10%.
On the other hand Analog Devices recommends to use FTDI chip connected to the SIN/SOUT(P1.0, P1.1) pins which has an internal 3.3-V voltage regulator with +-10% accuracy (min. 3.0V; typ. 3.3V; max 3.6V according to the FTDI FT232R datasheet).
Is 3.3 V voltage is guaranted by the silicon design (depends on gate oxide thickness in the input FETs)?
Would it be better to test ADuC706x and specify in the absolute maximum ratings +3.6 V as maximum?