Is it destructive to change the SCLK frequency while using SDRAM on the BF532? Is there a proper procedure for doing this, or is it forbidden altogether?
The restriction is on violating the timing spec. I think the BF537 manual has a better heading on the related explanations in EBIU chapter: "Changing System Clock During Runtime", although "Managing SDRAM Refresh During PLL Transitions" in BF533 manual seems to be similar.
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