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Refclk of AD9912

Question asked by durgaranibel on Feb 11, 2012
Latest reply on Feb 17, 2012 by Georgy

Ad9912 datasheet says that REFclk should be minimum of 632mVpp(each leg should have 316 mVpp). In our application we are converting single ended clock to the differential clock using a transformer(1 dB loss).

 

What is the level should be maintained in the single ended clock to drive the DDS?When differential input is used and when single ended is used?

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