In a design with BF526 I have assigned DR1SEC & DT1SEC to connect to a (mono) codec. Background: this is the optimal assignment for the application, when at least several SPI_SSEL pins should be available (the codec is a slave: Only 1 clock is needed - here TSCLK1 is unused. Since this pin function is in the same MUX group with DR1PRI, both signals must be inactive - I win two SPI_SSEL signals).
I'd appreciate to obtain some hints about the changes to a SOC-based sport initialisation and source code for codec/sport in order to establish this. In fact, I'd need double throughput to the TX-register, while on the receive side each second entry in the RX-fifo must be abandoned.