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Clarification on serial I/O in ADAU144x

Question asked by RyanJ on Feb 7, 2012
Latest reply on Feb 8, 2012 by RyanJ

I'm trying to verify my understanding that for ports which have both an input pin & output pin (SDATA_IN[3-8]/SDATA_OUT[3-8]), both the input AND output can be used simultaneously. E.g. I can use both SDATA_IN4 and SDATA_OUT4 at the same time. The requirement for allowing this is that clock domain 4 must be a slave, given:

 

Although a clock domain in slave mode can clock an arbitrary

number of serial ports, a clock domain in master mode can only

clock a single serial port. For Clock Domains[2:0] and Clock

Domains[11:9], the corresponding serial port is fixed as an input

or output. For assignable clock domains (Clock Domains[8:3]),

the corresponding serial port can be either an input or output,

depending on the setting of the clock pad multiplexer register


Is my above statement true? So in a system with a whole bunch of inputs, a whole bunch of outputs, and the DSP is the master of all clocks, I could tie all input devices off LRCLK0/BCLK0, and have all my inputs be slaved off of that (clock domain 0). For the outputs I could connect just LRCLK9/BCLK9 and slave the outputs from clock domain 9. Could you take it further and only use LRCLK3/BCLK3 (clock domain 3) and make everything (all input devices and all output devices) slaved from that? Configure the system as shown, only use the LRCLK3/BCLK3 pins, and still be able to use SDATA_IN[0-9] AND SDATA_OUT[0-9]?

 

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I feel like there's something I must be not understanding properly. Thanks,

-- Ryan

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