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ADV7171 timing question

Question asked by TimW Employee on Feb 7, 2012
Latest reply on Feb 7, 2012 by GuenterL

Looking in the data sheet @ figure 44 (page 35, timing register 1).  I see most of the settings are dependent upon Tpclk.  I can't find anywhere in the data sheet where Tpclk is defined.  Assuming it's the pixel clock, the settings for Vsync pulsewidth would appear to be way too short.  Is there something I'm missing here?