We are in a single conversion mode on the ADC7734. We set up the register to be in a single conversion mode with RDY set when any channel is ready. We set up the comm and mode register. After setting up the mode register, we poll the RDY signal. There are 3 channels we use. Basically, we set the 1st channel and poll for a RDY signal. When the RDY signal is asserted, we read the data and move on to the next channel.
We do have a timeout mechanism in place at the host processor. The processor will poll RDY for 100 ticks. It has been measured to take about 41 ticks for the RDY signal to assert. If RDY is not asserted by 100 ticks, we skip over the channel and move on to the next channel. On our 3rd channel, we wait for a certain period of time before reading the data after the setup. I believe we wait about 5 mS which should be plenty since the estimated conversion time is about 124 uS.
This seems to work but on an occasion, the RDY will not assert for any channel. It will remain high until a reset to the board. However, the processor will continue to get updated data from the ADC.