We have built a homemade board to control two AD9910s. Everything works except for synchronization; no combination of output sync receiver/input sync generator delays in the multichip sync register (0x0A) bring the SYNC_SMP_ERR outputs low, even momentarily.
Our sync circuit: SYNC_OUT from DDS1 connects into an 1-to-4 clock fanout buffer (ICS854104A); the input to the chip is 100-ohm terminated. LVDS pairs run from the buffer to the devices' SYNC_IN inputs (no additional termination is used, since I assumed SYNC_IN is internally 100-ohm terminated). The following screenshot shows the signal at the slave device's SYNC_IN ; it appears fine to me. (Ch. 3/4 (green/violet) = N/P, red = difference)
I have run through all the permutations of the output sync generator delay, input sync receiver delay and sync validation delay. Something appears to be getting through to the devices, as their relative sync_clk phases change for some settings; however these phase changes are sporadic and not reproducible.
I am out of ideas; am I missing something obvious? Please let me know if more details are needed.