We are developing a hardware that will be necessary a double access to the memory SRAM.
So many BF537 how much a FPGA they will have to have access (obviously at moments pre-defined) to this memory.
We are going to use the pins /BR, /BG and/BGH of the blackfin to control this access together with the FPGA.
However also we have a memory SDRAM in the same hardware and my doubts are:
1) Do I need to configure some register so that the signs /BR, /BG and /BGH works?
2) The core (CPU) is "halted" during the bus request or no? If my code is running in L1 during the bus request, what will happening?
3) I have to put SDRAM memory in self-refresh before grant the bus access, correct? To enter in self-refresh, I need to set the bits CDDBG and SRFS (EBIU_SDGCTL). But how can I know (firmware BF537) when the bus is returned? When FPGA finished, they set /BR and my code is already running or I must to do something, for example interrupt in I/O pin (PFx)?
4) We are using the ethernet (MAC) of the BF537. What will happen if a ethernet packet came (external interruption) when the blackfin did grant the bus? I would lose this interruption or from the moment that the FPGA to bring the bus back for the blackfin, would she be attended?
I accept sugestions.