AnsweredAssumed Answered

The minimum limitation value of PLL_DIV_RATIO value on ADV7842

Question asked by kamei Employee on Feb 6, 2012
Latest reply on Feb 7, 2012 by DaveD



I got one question of ADV7842 from my customer.

My customer is using the manual PLL_IDV_RATIO on their PC monitor application.

But they found the strange behaviour on their chassis and our ADV7842EB.

When customer changed the PLL_DIV_RATIO registers value to 443 or 442 on their chassis at 1080p 60Hz, the clamp voltage went to 0V.

I confirmed  this behaviour on ADV7842EB also. I attached file for this behaviour. Please see it.


So, my customer would like to know the minimum limitation of PLL_DIV_RATIO value on ADV7842.

And they would like to know the reason why the clamp voltage goes to 0V.


Thank you in advance,