I'm using the differential ADC driver AD8138 with a gain of 0.195 (Rf=390Ohm; Rg=2kOhm). It works obviously really fine on the PCB.

Then I read the Application Note AN-1026. In the chapter about the stability is mentioned that not all differential amplifiers can operate stable at fractional differential gains. I can't find this information in the datasheet of the AD8138.

Can the AD8138 operate stable at fractional differential gains in all circumstances?

Hello Marc,

I apologize for the belated reply, but we had some issues with the forwarding of questions from this forum.

I addressed the issues relating to stability of voltage- and current-feedback differential amplifiers in the Application Note you cited -- thank you for reading it; I hope you found the information there helpful. With the background from the Application Note in view, I will address your question regarding the AD8138, a

voltage-feedback(VF) differential amplifier.To find the phase margin for a VF amplifier, the amplifier's noise gain (non-inverting gain) in dB is plotted as a horizontal line on the open-loop gain magnitude and phase plots. The frequency at which the horizontal noise gain line and the open loop gain magnitude line intersect is the frequency where the magnitude of the loop gain = 0 dB, or equivalently one on the linear scale. We want to keep away from -180 degrees phase shift at this frequency in order to guarantee stability. The margin we have between our actual phase shift and -180 degrees at the frequency where the loop gain is 0 dB is the "phase margin." The AD8138 data sheet is quite old, and unfortunately does not contain open-loop gain and phase plots, but I have attached them here so you can perform your stability analysis.

The noise gain of the AD8138 is 1 + Rf/Rg, so for fractional differential gains the noise gain always lies between one and two (0 dB and 6 dB). You can see on the attached open-loop gain and phase plots that the AD8138 is indeed stable for some fractional diffrential gains. For example, for a differential gain of 0.2 V/V the noise gain is 1.2 V/V, or about 1.6 dB. From the attached plot you can see that the phase margin is about 45 degrees where the 1.6 dB noise gain line crosses the open-loop gain magnitude. (Please note that the attached plot indicates phase margin directly, so the ordinate scale is really "phase margin" or equivalently "phase + 180 degrees.") You can also see that the phase margin is dropping rather precipitously, so minimization of load and summing-node capacitances is extremely important.

Please feel free to contact me directly if you have further questions.

Best regards.

--Jonathan Pearson