We are using the ADuC7029 in Slave Mode with the master running at 400kHz. The processor speed is set to 10.4Mhz.
We are seeing if SCL is low (< 1.25usec), there is a delay by the ADuC7029, to “ACK”, creating a scenario on the bus called late ACK. What is the timing specification of the ACK once the address is recognized? The device is always operating as I2C slave and the interrupt is the only FIQ interrupt. All other interrupts are IRQ. Also there is no clock stretching in the system.
Attached is a scope shot which explains what we are seeing.