We have designed a quite complex board, with four TS201s on it. They are not connected into a cluster, rather each have their own memories, each 4 SDRAM Chips. Currently the board is under redesign because of the trouble caused by sourcing SDRAM memories. New board will have configurable SDRAM supply of 2.5V and 3.3V.
Currently we are making some IBIS simulations to check the Signal Integrity, meanwhile some measurements were done as well on the current board. The board is configured for 3.3V memories, type: MT48LC32M16A2
I am attaching 4 pictures. We are making some simulations/measurements on RAS line.
PCB.jpg - The current layout
IBIS_SCH - The extracted Hyperlinx schematics
IBIS_SIM - The simulated waveforms
SCOPE_CLK_RAS.png - The measured waveforms (at memory chip located at furthest (MEM14))
We are using the strongest drive (on the board too.), and models:
-ts201-7r.ibs from Analog Devices :-)
-y27b.ibs from Micron
The measured waveform is much "nicer" compared to to the simulation. Your IBIS modal says "Model has not been bench tested", but I expect closer results.
Can we trust simulation ?