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Conditional loads while DMA to memory-mapped FIFOs

Question asked by AndreasS on Jan 27, 2012
Latest reply on Feb 1, 2012 by AndreasS



we have a custom design with a bfin 537 running uClinux. We are performing reads and writes from/to a FPGA that is accessible via async memory interface. The some transfers are DMA transfers from/to FIFOs.


The programmers reference manual states under "Conditional Load Behavior" section that one should disable interrupts to avoid conditional loads in such situations. Our application runs in user mode and may not directly enable/disable interrupts (cli and sti instructions are supervisor mode only). We can observe at least extra read operations to our FIFOs causing trouble.


What is the preferred way for our application to disable interrupts? Is there a way the application can tell the bfin-dma driver to do this while the transfer is active? Looking at the drivers source it may use interrupts itself to indicate completion. So how is this to be handled?