I recently purchased a couple AD9523/PCBZ clock evaluation kits (http://www.analog.com/static/imported-files/user_guides/UG-169.pdf) for simple 40Mhz clock generation/distribution. Ideally I would like to have the signal generated onboard, but I can also use an external reference clock if necessary. After playing with the kit for quite a while, the closest output I can get is 40.0977Mhz, and I haven't been able to get it to use the reference input.
To get the 40.0977Mhz I use the VCXO at 122.88Mhz, which is then fed to PLL2 where the doubler is off, and the N divider A = 3 and B = 7. This gives a VCO of 3809.23, which I then divide by 5, then by 19 at the actual output.
Is the frequency of the onboard VCXO fixed?
How do I get it to use the REF_A input rather than the VCXO? Is it possible? Typically I can see under PLL READBACK that it detects REF A as OK, but it says "PLL1 Output Lock Detect: OFF (Clock Missing)".
So, in short, is there a way to use the AD9523 evaluation kit to generate 40Mhz outputs, either with or without an external reference clock?