At the moment I m in the confusion of selecting a DDS in the pool. As there are lot of devices one seem to be better than other.
My requirements are:
Low Jitter clock output: 70M Hz to 80 MHz
Clock resolution: 1kHz
Reconstruction Filter: Band Pass, Elliptic, f1 = 60 MHz, f2 = 90 MHz
Low Jitter clock will be further used as a clock to AD9265 (80MSPS) to digitalize the received data (~6MHZ).
Clock to the FPGA (where the demodulation done) will be generated from the same clock but at different frequeny using clock divider AD9513.
As of now i came to conclusion that one DDS is enough where REFCLK is 25MHz and in further i can use PLL multiplier for a higher SYSCLK.
Does the PLL include any phase noise? When is it to be considered?
I found AD9958 or AD9913 as a better choice. Is there any other ones to recommend?
Can you please tell me what does it mean Compliance Range(V) in DDS?
Thanks a lot in advance.