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AD9833 FSYNC Behaviour

Question asked by vrazik on Jan 24, 2012
Latest reply on Jan 25, 2012 by LiamR

I read through the datasheet but I would like some clarifcation on the behaviour of FSYNC.  Can FSYNC be held low for multiple 16bit SPI writes, or does it need to be taken high after each SPI write?  For example, is this a valid waveform: