I read through the datasheet but I would like some clarifcation on the behaviour of FSYNC. Can FSYNC be held low for multiple 16bit SPI writes, or does it need to be taken high after each SPI write? For example, is this a valid waveform:
It can work as standalone 16 active edge framing or multiple of 16 - see page 13 of datasheet.
So you could update output signal by :
Pull FSYNC Low - Freq 0 LSB Data + Freq 0 MSB Data - Pull FSYNC Hi.
Retrieving data ...