During V_LOCKED_RAW=1 and DE_REGEN_LCK_RAW=1, customer read the following register for video format detection in HDMI mode.
( Customer is using the interrupt status of them as trigger. so, customer checked these RAW bits after interupt event.
Of course, V_LOCKED_RAW, DE_REGEN_LCK_RAW bits kept "1 " at that time.)
But customer did not get correct readback value in them at that time.
After waiting 300msec, they could get the correct value. But they are no sure why they need to wait.
And they would like to reduce this wait period.
Could we expect this behaviour?
( Questions )
1. Why did customer need to wait reading register value during V_LOCKED_RAW=1 and DE_REGEN_LCK_RAW=1.
2. Minimum wait time for reading vertical parameters. 300msec is tentative value at customer.
HDMI_MAP ADDR 0x0B Bit INTERLACED_HDMI
HDMI_MAP ADDR 0x07-08 Bit[11:0] LINE_WIDTH[11:0]
HDMI_MAP ADDR 0x09-0A Bit[12:0] FIELD0_0_HEIGHT[12:0]
HDMI_MAP ADDR 0x0B-0C Bit[12:0] FIELD1_1_HEIGHT[12:0]
HDMI_MAP ADDR 0x1E-1F Bit[11:0] TOTAL_LINE_WIDTH[11:0]
HDMI_MAP ADDR 0x26-27 Bit[12:0] FIELD0_TATAL_HEIGHT[12:0]
HDMI_MAP ADDR 0x28-29 Bit[12:0] FIELD1_TATAL_HEIGHT[12:0]