We are currently using the AD9910 DDS. Our ref clock is 20 MHz and multiplier is 50 to generate a 1 GHz System clock. When I generate
any frequency a 2.5 MHz spur sits around the main carrier. Why is this? Is there a way to get rid of it?
I have tried changing the PLL divider but still the same, aslo the VCO etc. There is no 2.5 Mhz clock on our ref clock which is clean.