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AD9628 valid data window for FPGA

Question asked by PetrFirsov on Jan 20, 2012
Latest reply on Jan 25, 2012 by DougI


I need to use a 125MHz ADC with Spartan-6. I chose the AD9628-125.

I do not understand switching specifications

Data Propagation Delay (tPD) 2.4 ns
DCO Propagation Delay (tDCO) 2.4 ns
DCO to Data Skew (tSKEW) -0.20 ... +0.03 ... +0.25 Ns

In  order for this ADC fit the parameters of time, I must see that the  window of valid data on the ADC output is greater than Tsetup + Thold on FPGA input. Also I will include in the calculation of various jitter.

And what is it, that window? I have only the relationship between clock (DCO) and data.
We assume the data will be valid for-0.25ns (or through +0.2 ns) to switch the output clock signal. But in the datasheet is no information about how many ns after switching  the output clock data will no longer be valid and will switch to the  next word. So I do not know the actual data size of the window, just like I do not know the time of metastability of the data.

I watched the ADC from Texas. They  have a different system of switching specifications - indicates Tsetup and Thold for outputs, which provides the chip relative to the rising/falling edge of his  clock.
And here it is not clear ..

And the second question:
What is a reserve for Tsetup and Thold input FPGA must have in order to guarantee receive the data from the ADC. + / - 10% of the time is enough?