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weird BF532 SPORT problem

Question asked by TDS on Jan 19, 2012
Latest reply on Jan 25, 2012 by PGaganoff

I have created a data acquisition system comprised of a daisy-chain of four ADS1178 8-ch A-Ds for a total of 24 channels.   I am interfacing the BF532 to these A-Ds through SPORT0.  I am passing the data stream through a 60Hz IIR notch filter and running at a fairly slow rate of 256 samples per second.  Everything is working fine and my application program displays a nice scrolling graphic display of the 24 analog input channels.   BUT ... once every 10 seconds (ie, once every 2560 samples) I get a major data glitch that rings the filter and produces a big transient artifact.


What I have done so far is:


-  At first I thought it was related to some characteristic of the filter.   So, I created a sinewave table of synthesized data and fed that to the filter on each interrupt to provide a simulated data stream instead of actual A-D data.   With that, everything is fine and there is not glitch.  So, I am sure this is not realted to the filter.


-  I thought it might be related to the DMA, and so I have operated the SPORT in both DMA and non-DMA modes, and I still get the glitch every 2560 samples in both cases.


-  I thought something might be going on with the A-D converters ... I captured the A-D converter output with my logic analyzer and inspected the data at the time the glitch occurs, and the A-Ds are providing good data.


So, I have come to the conclusion that the source of the problem must be within the SPORT interface itself.


I am initializing the SPORT like this:


*pSPORT0_TCR1 = 0x0000;                         // disable SPORT0 TX
*pSPORT0_RCR1 = 0x0000;                         // disable SPORT0 RX


*pSPORT0_RCLKDIV =0x01F;                        // serial clock divider (5.2500MHz / 8) = 656,250Hz
*pSPORT0_TCLKDIV =0x01F;                       


*pSPORT0_RFSDIV = 0xA00;                        // frame sync divider = 2560 clock cycles
*pSPORT0_TFSDIV = 0xA00;   


*pSPORT0_RCR2   = 0x000F;                       // set RX word length to 16
*pSPORT0_TCR2   = 0x000F;                       // set RX word length to 16

*pSPORT0_RCR1   = 0x6206;                       // Internal clock, internal frame sync,
*pSPORT0_TCR1   = 0x6206;
*pSPORT0_MCMC1 = 0x2000;                        // window size = 24 channels, offset = 0
*pSPORT0_MCMC2 = 0x1010;                        // no frame delay, normal sync, mulitchannel enable, no packing
*pSPORT0_MRCS0 = 0x0FFFFFF;                  // enable channels 0 to 24


I am running with a 30MHz CLKIN, and I change the PLL multiplier to 7.   I end up with a Serial Clock of 5.25Mhz, and in my SPORT initialization I use a divider of 8 to produce a SPORT clock of 656,250.    The A-D converter then generates a sample rate a Clock/2560 .... so I set the frame sync divider to 2560 to produce a frame sync at 256 per second.


This is all working great, just as it is supposed to, on the scope all the signals are great, and the logic analyzer shows good consistent output from the A-Ds, I get a good graphic display of the data in my application ..... But, once every 10 seconds I am getting a data glitch that I cannot determine where it is coming from, and it seems to be originating in the SPORT.


Is it just a coincidence that I am using a "Frame Sync Divider" of 2560 to generate a frame sync once every 2560 SPORT clock cycles ... AND .... I also seem to be having a strange artifact that is occuring once every 2560 data samples ??


I am really at a loss of where to go from here??   Everything is working great, but it is not useable with this once-every-ten seconds artifact.


Any thoughts will be greatly appreciated.