We just ran into an overlooked timing issue in our design using the AD7685. An external device which is generating the CNV line is holding it high for ~2.6us and therefore CNV is high at the past the maximum conversion time (2.2us) and therefore SDO is not going low at the end of conversion. If D15 is low, then that is seen as the end of busy and we read data correctly. If D15 is high, then we never generate an SCLK to acquire data.
The data sheet says CNV "must be returned low before the minimum conversion time and held low until the maximum conversion time to guarantee the generation of the BUSY signal indicator." Does CNV truly have to be low from 500ns to 2.2us after CNV goes high? We can probably shorten CNV but may not be able to get it below 500ns. When is the state of CNV sampled to determine whether or not to bring SDO out of hi-Z and into a low state, or is it at the end of conversion, which could be anywhere between 500ns and 2.2us dependent on when the internal comparator is balanced, as I suspect?