Does any experience connecting 8chn/18bit ADC Ad7608 to ADSP21065 Processor??
Thanks. I understand your point about the TFS signal. I think one more way could be to keep the TFS signal data independent and connect the busy signal of the ADC to an IRQ interrupt of the DSP. The data can be read via SPORT inside the IRQ ISR.
Regarding your second question, I was going through the AD7608 data sheet and found the following statement:
" For the AD7608 to access all eight conversion results on one DOUT line, a total of 144 SCLK cycles are required. These 144 SCLK cycles can be framed by one CS signal or each group of 18 SCLK cycles can be individually framed by the CS signal".
How about using the RFS signal in late frame sync mode instead of early frame sync mode and making it active low instead of active high ? This will make sure that the RFS is low only for SLEN+1 - 18 CLK cycles for each word.
I've moved this question to the SHARC Processors community to see if anyone in this community has any experience with this connection.
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Thank You, if any answer, that would be great help.
I think, EE-259 and EE-260 might be helpful. They are available at the link below:
Hope this helps. Please let me know if you have any further specific questions.
Many thanks about Your suggestion, but my main interest is to
connect ADC with DSP using serial communication
whic is availabel on both parts, to say using SPORT DSP interface
to AD7608/9 serial option (-PAR/SER=1).
It seems to me that these componets can be connected directy
DSP would generte clock signal (RCLK) connect ot -RD/SCLK (ADC
and framing signal(RFS) to be connected to -CS (ADC pin),
but the other mebers experience would be well-come.
For serial ADC interface with ADSP-21065L, you might refer to EE-247 available at the link below:
Many thanks Mitesh. It seems that Your suggestion about
EE-247v01.pdf is the appropriate answer. Even that in EE-247, ADC
is "master" (generator of the clock signal, and the frame signal),
while on AD7608/9 such possibilities are not implementet, so that
is why I think that SPORT: RFS, and RSCLK has to be generated by
the ADSP21065 and can be used for 'handshake" signals betwwen ADC
and DSP. Good idea in EE-247, is the usage of TFS signal, as a
kind of control for 'starting the ADC conversion', off course
everythink with a appropriate software support.
It is unexpected for me that in Analog Dev. Technical support,
that they do not have EE suggestion for AD7608/9 interconnection
with ADSP using SPORT.
Thanks for your reply. I do understand your question and concerns better now. I went throught the the data sheet of AD7608 and below is what I think can be one way to implement this interface:
1) TFS can still be used to generate periodic "convert start" as mentioned in EE-247.
2) SCLK can be generated internally via SPORT and connected to the /RD signal of the ADC.
3) RFS can be generated internally via SPORT in active low, late frame sync mode and thus can be used as /CS to the ADC.
4) Busy signal from the ADC can be connected to any of the /IRQx input of the processor in edge sensitive mode.
SPORT can be enabled inside the IRQx ISR, single word can be read in core/DMA mode, and then the SPORT can be disabled again.
I hope this might give you a high level overview of the interface. Please let me know if you still have any specific questions.
In case you want to read all the four/eight words (V1,V2,V3....V8), you might have to configure the SPORT in multichannel mode. So, instead of late frame sync mode, you will have to configure MFD = 0 and inside the ISR, you might do a DMA of four or eight words to read the data corresponding to each channel.
Hope this helps.
Your answers are exactly what I am expecting to be mine
application. The only hesitation was about whether RFS ('late
direct connection to /CS ADC7608 would be correct in order to, how
to say ,"burst read" of all 8 ADC channels,
because ADC would send the data bits in "packet burs of 8 x 18
Using DMA (8 words packet, and then Interrupt Request in order to
'disable' SPORT is the most efficient time consumption solution
that has been "in mind" too.). Off-course 'muli-channel mod' can
be applied too, but I would prefer if possible
channel-by-channel reading (just for easier hardware debugging).
As I understand AD7608 data sheet, clock signal while \CS is
logical high, has no influence on shifting the data bits, so for
each channel 19 RCLK clock periods would be spent for each channel
word-data reading form ADC to ADSP ( totaly 8 x 19 RCLKs, that
would "last" about 76us for 2MHz RCLK, or about 19us for 8MHz
to that value has to be addede about 4us for conversion, if
"conversin and then read data mode" is selected ).
Concerning that sampling frequency has to be as stabile as
possible, from one side, and an intention to design as 'easier'
as possible design, I think that TFS (generated by ADSP) can be
used as 'start of conversion' signal' ( Minimum CONVST x high
pulse > 25ns)
if timing clock for transmitter can be different then receiver
clock (for the same SPORT, as "divisor" registers TDIVn is
independent from RDIVn).
If this is "the case", and concerning that the time for conversion
is almost constant (from 3.45us to 4.15us, without 'over-sampling
transmission of 'dummy word' from SPORT (with DMA support) can
produce stabile sampling frequency (I would expect).
I now wonder if it is possible (with some "manipulation of"
trasmiter, such as 'transmitr serial word length',;trasmiter
clock' and , TFSDivisor, etc.. )
to get an interrupt from trasmitter that wouold correspond to
"end of converson time" , or lasts a bit more, in order not to use
/IRQ pin (signal) of the ADSP,
while TFS would activate "CONVSTart".
I thought about it and realized that you may not be able to use TFS as convert start when the SPORT is configured in multichannel mode as it becomes TDV(Transmit Data Valid) signal in this mode. You could instead use one the programmable timer to generate periodic convert start signal at the PWM_EVENTx pin. Inside the ISR of this timer, you can start another timer to generate interrupt after the worst case conversion time is over (4 us). Inside the ISR of the second timer interrupt, you can enable the SPORT in multichannel mode, read the eight words one by one, and then disable the SPORT to de-asssert the RFS signal connected to the /CS. This process can continue forever.
Yes, you can use core mode as well to read the 8 channels one by one. You can read the CHNL (28-24 bits) of the STCTLx register to identify the currently selected channel information.
My idea is to use SPORT not in multichannel mod, but i standard early RFS mod,
so for every channel one RFS signal, and transmit dummy short words, with the transmit clock much lower then receive, so TFS signal would last enough long to satisfy ADC timing, with desired sampling frequency.
Thanks for the clarification. In that case, you may configure the TFS signal as data independent by setting the DITFS (bit 15) of the STCTL register. With this, the TFS signal will occur periodically irrespective of whether the data is fed to the TX buffer or not.
Yes, that is one side of the "idea", but signal "TX- buffer empty" (so dummy transmission has to last longer then A-to-D conversion) would have to generate an interrupt-routine that would 'enable' SPORT receiver part to start receiving AD7608/9, 8-channels data with consecutive 8 (18bits) data-words ( say with DMA support ).
I expect that first RFS would initially start "data-burst" from ADC, but I only wonder if timing of "early RFS" (programmed to receive 18-bits word) would be correct way for ADC data reception, because of some kind of ADC data-stream 'interruption' while RFS signal 'goes' high-after 18 clock signal, so the first bit for consecutive (next) channel would be 'interrupted as RFS goes high" ( I wonder if such timing would make some "interference" to ADC internal timing in data stream). It seems to me from AD7608/9 data-sheet that there would be no problem, but some kind of experienced user would be well-come.
Concerning yours: "....How about using the RFS signal in late frame sync mode instead of early frame sync mode and making it active low instead of active high ? This will make sure that the RFS is low only for SLEN+1 - 18 CLK cycles for each word. ..."
That is VERY GOOD suggestion.
As I understand then RFS would be minimum one CKL `high' before next word read can happen, depending on the desired number of serial clock cycles between frame synch pulse ( defined by RFSDIV ).
After all I think that AD7608/9 can be connected directly to the ADSP21065, while DSP would generate serial clock timing and \CS signal for reading the data from the ADC, and TFS can be used as a kind of stat of the conversion control signal.
Thank You very much for the useful assistance. I believe that one day Analog Devices would make an official , so called "EE-note" about connection AD7608/9 to SPORT interface.
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