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Framing SPORT SDO with external FS

Question asked by Ed1632 on Jan 16, 2012
Latest reply on Jan 19, 2012 by Mitesh

I am modifying some third party ADSP-21479 code to use different ADC's and DAC's; I am having trouble changing the DAC serial length from 18 bits to 16 bits. I am not sure if the error is due to a DSP problem with the serial length, or a DAC problem with the improperly framed data (or something else entirely- I have for instance adjusted the level of the input looking for overflow conditions, but reducing the input level does not seem to help).

My suspicion is that it is a framing problem-  I was under the impression that the SPORT data transmit is framed by the SPORT_FS_I, but this does not seem to be the case. (see below)

Can you tell me how to adjust the timing of the serial data transmission so that it occurs between frame synch pulses?

 

We are using an external clock driving the Precision Clock Generators; PCG_FSC_O and PCG_CLKC_O are driving the SPORT(0,2)_FS_I  and SPORT(0,2)_CLK_I, as well as the CLCK and FS inputs on the DAC. I have adjusted the pulse width of the FS such that 16 clock edges occur between the falling and rising edge.

I have changed the SLEN in  sport control registers, i.e.:

*pSPCTL0 =      SCHEN_A | SDEN_A | SPTRAN | BHD | SLEN16 | SPEN_A | FSR ;//| CKRE  | ICLK| IFS;

*pSPCTL2 =      SCHEN_A | SDEN_A | SPTRAN | BHD | SLEN16 | SPEN_A | FSR ;//| CKRE  | ICLK| IFS;

 

Observing the control and data signals at the DAC, the data now overlap the FS signal:

BadDAC.jpg

Data(SDI): Yellow; CLCK: Magenta; FS: Blue; LDAC: Green

 

And the output is missing half-cycles:

BadDACout.jpg

Data(SDI): Yellow; CLCK: Magenta; FS: Blue; DAC Vout: Green

 

For Comparison, the 18 bit case is shown below. This appears to work fine:

GoodDAC.jpg

Data(SDI): Yellow; CLCK: Magenta; FS: Blue; LDAC: Green

 

I'd appreciate any advice or suggestions you might have.

Thank you in advance,
Ed

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