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BF506F ACM settings and ACM outputs on Scope

Question asked by odemirci on Jan 16, 2012

Hello,

 

I am using BF506F EZ KIT LITE. I use TIMER7 to trigger the ACM. TIMER7 has TIMER_WIDTH od 0.4us and TIMER_PERIO=50us. TIMER7 works as expected and its output checks okay on the scope. I set the ACM registers as shown below. I do observe the ACM interrupt.  However I am having problem seeing the ACM outputs such as CS\, ASCLK, RANGE, SGL/DIFF\, or A[2..0]. Does anyone have an idea why I do not see the ACM outputs on the scope?

 

Note: On the program list below please ignore SPORT1 and DMA4 for settings. They will be used after I make ACM works fine. Whole purpose is to check A2D.

 

Thank you for your time and help,

 

Osman Demirci

 

/////////////////////////////////////////////////////////////////////////////
// File Name: A2D.asm
// Date: 07 Ocak 2012
////////////////////////////////////////////////////////////////////////////
// PF0 --> LED2
// PF1 --> LED3
// PF2 --> LED4
// PF3 --> PB0
// PF4 --> PB1

     
#include <defBF506F.h>
#include <defBF50x_base.h>

#define Xa 7
#define Ya 213

.SECTION L1_data;

.BYTE2 spare1=0;
.BYTE2 spare2=0;
.BYTE2 rx_buf[12]={1,2,3,4,5,6,7,8,9,10,11,12};

//.BYTE2  zenith[256]="zenith16.dat";    // 16-bit zenith data
//.BYTE2  azimuth[256]="azimuth16.dat";  // 16-bit azimuth data

// Mark the beginning of a logical section mirroring an array of contiguous
//   locations in processor memory. Statements between one '.SECTION' and the
//   following '.SECTION' directive comprise the contents of a section. Here,
//   we place the global symbol '_main' and the associated code into the
//   'program' section.
.SECTION program;
.VAR prog_memory_var=0; // always 32-bit

// The .ALIGN directive forces the address alignment of an instruction or
//   data item. Here, ensure the first element of the section is aligned.
.ALIGN 4;


// Set the scope of the '_main' symbol to global. This makes the symbol
// available for reference in object files that are linked to the current
// one. Use '.EXTERN' to refer to a global symbol from another file.
.GLOBAL _main;

// Declare the '_main' symbol.
_main:

// START: SET CCLK and SCLK
// Bit0=0 DF (Divide Frequency) (0: DF=1, 1:DF=2)
// Bit1=0 PLL_OFF (0=Enable PLL control,1=Disable)
// Bit2=NC
// Bit3=0 STOPCK (0=CCLK on, 1=CCLK off)
// Bit4=NC
// Bit5=0 PDWN (All internal clocks: 0=on, 1=off)
// Bit6=NC
// Bit7=NC
// Bit8=0 BYPASS (0=do not bypass PLL, 1=bypass PLL)
// Bit9-14=4 MSEL (Multiplier Select)
// Bit15=NC
// 0x0mmm mmm0 1000 0000
// 0x0000 1000 1000 0000 = 0x0880

// External Clock is running at 25MHz
// fVCO=25MHz*MSEL=25MHZ*4=100MHz
  P0.L=LO(PLL_CTL);
  P0.H=HI(PLL_CTL);
  R0.L=0x0880;      
  W[P0]=R0.L;


  // Bit4-5=00 CSEL: 00=VCO/1, 01=VCO/2, 10=VCO/4, 11=VCO/8
  // fCCLK=fVCO/CSEL, fCCLK=100MHz/1=100MHz (0.01us)
  // Bit0-3=4  SSEL :1 to 15
  // fSCLK=fVCO/SSEL, fSCLK=100MHz/4=25MHz (0.04us)
  // 0x0000 0000 00cc ssss
  // 0x0000 0000 0000 0010 = 0x0002
  // with these setup I measured fsclk=25MHz therefore fVCO must be 100MHz
  P0.L=LO(PLL_DIV);
  P0.H=HI(PLL_DIV);
  R0.L=0x0005;      
  W[P0]=R0.L;
 
  // Voltage Regulator Control Register
  // used for seeing fsclk on TP1 with scope
  // Bit0-7 Reserved
  // Bit12=1, Bit13=1
  // Bit14=1 1=Enable EXTCLK pin, 0=Disable EXTCLK pin
  P0.L=LO(VR_CTL);
  P0.H=HI(VR_CTL);
  R0.L=0x70B0;      
  W[P0]=R0.L;

// START: SET BF506F PINs 
  P0.L=LO(PORTF_FER); // 0xFFC0 3200: Port F Function Enable Register
  P0.H=HI(PORTF_FER); // 0:GPIO mode,1:Enable peripheral function
  R0.L=0x0400;        // pin10 is enabled for peripheral function (TIMER2)
  W[P0]=R0.L;

  P0.L=LO(PORTF_MUX); // 00= 1st peripheral function
  P0.H=HI(PORTF_MUX); // 01= 1st alternate peripheral function
  R0.L=0x0400;        // 10= 2nd alternate peripheral function
  W[P0]=R0.L;         // set bit11&10=01 for TMR2
 
  P0.L=LO(PORTFIO_DIR);  // 0xFFC0 0730:GPIO Direction Registers
  P0.H=HI(PORTFIO_DIR);  // 0:input, 1:output
  R0.L=0x0007;           // PF0=LED2,PF1=LED3,PF2=LED4 is outputs
  W[P0]=R0.L;            // PF3=PB0, PF4=PB1 and rest are inputs

  P0.L=LO(PORTFIO_INEN); // 0xFFC0 0740:GPIO Input Enable Registers
  P0.H=HI(PORTFIO_INEN); // 0:Input Buffer Disabled, 1:Input Buffer Enabled
  R0.L=0x0418;           // PF3 and PF4 are buffered inputs
  W[P0]=R0.L;            // PF3==PB0 and PF4=PB1
                         // Enable PF10=32768Hz Clock for TIMER2  
 
  // set port f polarity register
  // 0=rising edge, 1=falling edge
  P0.L = LO(PORTFIO_POLAR); // 0xFFC0 0734
  P0.H = HI(PORTFIO_POLAR);
  R0.L = 0x00000;
  W[P0] = R0.L;
 
  // set port f sensetivity register
  // 0=Level, 1=Edge (if not edge then you get interrupt all time)
  P0.L = LO(PORTFIO_EDGE);
  P0.H = HI(PORTFIO_EDGE);
  R0.L = 0x00008; // PF3 is edge sensetive
  W[P0] = R0.L; 
 
// END: SET BF506F PINs   
//////////////////////////////////////////////////////////////////////////////

 

 


//////////////////////////////////////////////////////////////////////////////
// START: setting ACM Parameters
// Set ACM_TC0 and ACM_TC1 registers
// fSCLK=25MHz (0.04us)
// Bit[7..0]=00, CLKDIV
// Bit15..8]=02, TS (Setup Cycle * fSCLK)
// 0xbbbb bbbb bbbb bbbb
// TS=2*fSCLK (0x02) and CKDIV=0 (0x00) thus fACLK=fSCLK/2=12.5MHz (0.08us)
P0.L = LO(ACM_TC0); // 0xFFC0 3104
P0.H = HI(ACM_TC0);
R0.L = 0x0200; 
W[P0] = R0.L;
// TZ=15*fACLK (0xF), TH=4*fACLK (0x4) and TCSW=32*fACLK (0x20)
P0.L = LO(ACM_TC1); // 0xFFC0 3108
P0.H = HI(ACM_TC1);
R0.L = 0xF420; 
W[P0] = R0.L;

// Set ACM Event Control Register:
// A[2..0], RANGE=1 (Vin=0V to 5V), SGL/DIFF=1 (SGL), Bit0=1 (Enable)
// 0xnnnn nnnn nnsr aaae
// 0xnnnn nnnn nn11 0001
P0.L = LO(ACM_ER0);  // 0xFFC0 3120
P0.H = HI(ACM_ER0);
R0.L = 0x0031;     // Enable, select channel1, Range=1, SGL/DIFF=1
W[P0] = R0.L;

P0.L = LO(ACM_ER1);  // 0xFFC0 3124
P0.H = HI(ACM_ER1);
R0.L = 0x0033;     // Enable, select channel2, Range=1, SGL/DIFF=1
W[P0] = R0.L;

P0.L = LO(ACM_ER2);  // 0xFFC0 3128
P0.H = HI(ACM_ER2);
R0.L = 0x0035;     // Enable, select channel3, Range=1, SGL/DIFF=1
W[P0] = R0.L;

P0.L = LO(ACM_ER3);  // 0xFFC0 312C
P0.H = HI(ACM_ER3);
R0.L = 0x0037;     // Enable, select channel4, Range=1, SGL/DIFF=1
W[P0] = R0.L;

P0.L = LO(ACM_ER4);  // 0xFFC0 3130
P0.H = HI(ACM_ER4);
R0.L = 0x0039;     // Enable, select channel5, Range=1, SGL/DIFF=1
W[P0] = R0.L;

P0.L = LO(ACM_ER5);  // 0xFFC0 3134
P0.H = HI(ACM_ER5);
R0.L = 0x003B;     // Enable, select channel6, Range=1, SGL/DIFF=1
W[P0] = R0.L;

// Set ACM Event Timer Control Register (32-bit)
P0.L = LO(ACM_ET0);  // 0xFFC0 3180
P0.H = HI(ACM_ET0);
R0.L = 0x0002;       // Evet0 Timer
R0.H = 0x0000;
[P0] = R0;

P0.L = LO(ACM_ET1);  // 0xFFC0 3184
P0.H = HI(ACM_ET1);
R0.L = 0x0037;       // Evet1 Timer
R0.H = 0x0000;
[P0] = R0;

P0.L = LO(ACM_ET2);  // 0xFFC0 3188
P0.H = HI(ACM_ET2);
R0.L = 0x006C;       // Evet2 Timer
R0.H = 0x0000;
[P0] = R0;

P0.L = LO(ACM_ET3);  // 0xFFC0 318C
P0.H = HI(ACM_ET3);
R0.L = 0x00A1;       // Evet3 Timer
R0.H = 0x0000;
[P0] = R0;

P0.L = LO(ACM_ET4);  // 0xFFC0 3190
P0.H = HI(ACM_ET4);
R0.L = 0x00D6;       // Evet4 Timer
R0.H = 0x0000;
[P0] = R0;

P0.L = LO(ACM_ET5);  // 0xFFC0 3194
P0.H = HI(ACM_ET5);
R0.L = 0x010B;       // Evet5 Timer
R0.H = 0x0000;
[P0] = R0;


// Set ACM Event Interrupt Mask (Enable) Register
// Use Single-Shot Sequencing Mode (Event0 to Event5 are executed)
// Therefore I use Event5 to generate an interrupt
P0.L = LO(ACM_IMSK);  // 0xFFC0 3114
P0.H = HI(ACM_IMSK);
R0.L = 0x0020;     // 0x0020=Event5 interrupt generation is enabled
W[P0] = R0.L;

// Enable ACM interrupt
// SIC_IMASK1=0xbbbb bbbb bbbb bbba abbb bbbb bbbb bbbb
// Bit16= ACM interrupt, Default priority=3 (IVG10)
P1.L = LO(SIC_IMASK1);  // 0xFFC0 014C
P1.H = HI(SIC_IMASK1);
R0 = [P1];
BITSET(R0, 16); // Bit16=1
[P1] = R0;

// initiate ACM Interrupt
// Default SIC_IAR6[3..0]=3 (IVG10=EVT10) interrupt priority
P1.L = LO(IMASK);  // IMASK 0xFFE0 2104: Interrupt Controller
P1.H = HI(IMASK);
R0.L = LO(ACM_isr);
R0.H = HI(ACM_isr);
[P1 + EVT10 - IMASK] = R0; //EVT10(0xFFE0 2028) ün içine ACM_isr in adresini yaz
R0 = [P1];
BITSET(R0, 10); // Enable ACM interrupt
[P1] = R0;

// Set ACM Control Register
// Bit0=0, Enable(1)/Disable(0): Do not set it yet
// Bit1=1, ACMTMR0EN Enable(1)/Diasable(0)
// Bit2=0, ACMTMR1EN Enable(1)/Diasable(0)
// Bit4&3=11, TRGSEL0 (11=select TMR7)
// Bit6&5=00, TRGSEL1 (11=select TMR7)
// Bit7=1, TRGPOL0 (0=Rising Edge trigger)
// Bit8=0, TRGPOL1 (0=Rising Edge trigger)
// Bit9=0, CSPOL (0=Active low CS\)
// Bit10=0, CLKPOL (ACLK polarity)(0=ACLK falling edge occurs after CS\ active)
// Bit11-12-13 not defined
// Bit15&14=01, EPS (01=SPORT1, 00=SPORT0)
// 0x0100 0000 1001 1010 = 0x409A
P0.L = LO(ACM_CTL); // 0xFFC0 3100
P0.H = HI(ACM_CTL);
R0.L = 0x409A;  // ACM is not enabled here it will be later
W[P0] = R0.L;
// END: setting ACM Parameters
//////////////////////////////////////////////////////////////////////////////

/*
//////////////////////////////////////////////////////////////////////////////
// START: setting SPORT1 Parameters
// Set SPORT1 Receive Serial Clock Divider Register
P0.L = LO(SPORT1_RCLKDIV);  // 0xFFC0 0928
P0.H = HI(SPORT1_RCLKDIV);
R0.L = 0x0000; 
W[P0] = R0.L;

// Set SPORT1 Receive Frame Sync Divider Register
P0.L = LO(SPORT1_RFSDIV); // 0xFFC0 092C
P0.H = HI(SPORT1_RFSDIV);
R0.L = 0x0000; 
W[P0] = R0.L;

// Set SPORT1 Receive Configuration1 Register
// Bit0=0, 0:Disable 1:Enable
// Bit1=0 0:External 1:Internal Receive Clock
// Bit3&2=00 means Data formating type select: Zero Fill
// Bit4=1, 0:Receive MSB first, 1:Receive LSB first
// Bit9=0, 0:External RFS, 1:Internal RFS used
// Bit10=1, 0:Does not require RFS, 1:Require RFS for every data word
// Bit12=1, 0:Active High RFS, 1:Active Low RFS
// Bit13=0, 0:Early Frame Syncs, 1:Late Frame Syncs
// Bit14=0
// 0x15 14 13 12   11 10 9 8   7 6 5 4    3 2 1 0
// 0xn   b  b  b    n  b b n   n n n b    b b b b
// 0xn   0  0  1    0  1 0 0   0 0 0 1    0 0 0 0
P0.L = LO(SPORT1_RCR1);  // 0xFFC0 0920
P0.H = HI(SPORT1_RCR1);
R0.L = 0x1410; 
W[P0] = R0.L;

// Set SPORT1 Receive Configuration2 Register
// Bit[4..0]=8, SLEN: Sport Word Lenght
// Bit8=1, Secondary side 0:Disabled, 1:Enabled
// Bit9=0, Receive Stereo Frame Sync Enable 0:Normal, 1:Frame Sync becomes LR clock
// Bit10=0, 0: Left, 1:Right stereo channel first
// 0x15 14 13 12   11 10 9 8   7 6 5 4    3 2 1 0
// 0xn   n  n  n    n  b b b   n n n b    b b b b
// 0xn   n  n  n    n  0 0 1   n n n 0    1 0 0 0
P0.L = LO(SPORT1_RCR2);  // 0xFFC0 0924
P0.H = HI(SPORT1_RCR2);
R0.L = 0x0108; 
W[P0] = R0.L;
// END: setting SPORT1 Parameters
//////////////////////////////////////////////////////////////////////////////

 

//////////////////////////////////////////////////////////////////////////////
// START: DMA4 SETTINGS (for SPORT1 Receive)
P0.L = LO(DMA4_X_COUNT);  // 0xFFC0 0D10
P0.H = HI(DMA4_X_COUNT);
R0.L=0x000C; 
W[P0] = R0.L;

P0.L = LO(DMA4_X_MODIFY);  // 0xFFC0 0D14
P0.H = HI(DMA4_X_MODIFY);
R0.L=0x0001; 
W[P0] = R0.L;

P0.L = LO(DMA4_START_ADDR); // 0xFFC0 0D04
P0.H = HI(DMA4_START_ADDR);
R0.L = LO(rx_buf);  // Read rx_buf address value
R0.H = HI(rx_buf);
[P0] = R0;  // Write rx_buf address value to DMA4_START_ADDR register

// Bit[14..12]=1 means Autobuffer operation
// Bit7=1 Allow complition of work to generate a data INTERRUPT
// Bit5=1 Syncronized transition
// Bit3&2=01 16 bit transfer
// Bit1=1 DMA is memory write operation
// Bit0=0 Enable(1) / Disable(0) DMA channel
// 0x15 14 13 12   11 10 9 8   7 6 5 4    3 2 1 0
// 0xn   b  b  b    b  b b b   b b b b    b b b b
// 0xn   0  0  1    0  0 0 0   1 0 1 0    0 1 1 0
P0.L = LO(DMA4_CONFIG); // 0xFFC0 0D08
P0.H = HI(DMA4_CONFIG);
R0.L=0x10A6;  // DMA is not enabled here
W[P0] = R0.L;


// DMA4 (SPORT1_RX) Interrupt settings
// SIC_IMASK0=0xbbbb bbbb bbbb bbbb bbbb bbbb bbbb bbbb
// Bit18 of SIC_IMASK0 is for DMA4 enable
P1.L = LO(SIC_IMASK0);  // 0xFFC0 010C
P1.H = HI(SIC_IMASK0);
R0 = [P1];
BITSET(R0, 18); // Bit18=1
[P1] = R0;


// initiate DMA4 Interrupt
// Default SIC_IAR2=0x3333 2222 (0xFFC0 0118)
// DMA4 default is SIC_IAR2[11..8]=2 (EVT9 priority)
P1.L = LO(IMASK);  // IMASK 0xFFE0 2104: Interrupt Controller
P1.H = HI(IMASK);
R0.L = LO(DMA4_isr);
R0.H = HI(DMA4_isr);
[P1 + EVT9 - IMASK] = R0; // EVT9(0xFFE0 2024) ün içine DMA4_isr in adresini yaz
R0 = [P1];
BITSET(R0, 9); // Enable DMA4 interrupt
[P1] = R0;
// END: DMA4 SETTINGS (for SPORT1 Receive)
//////////////////////////////////////////////////////////////////////////////
*/


//////////////////////////////////////////////////////////////////////////////
// START: TIMER7 setup and interrupt
  // Setup PORTG (PG5=TIMER7)
  P0.L=LO(PORTG_FER); // 0xFFC0 3204: Port G Function Enable Register
  P0.H=HI(PORTG_FER); // 0:GPIO mode,1:Enable peripheral function
  R0.L=0x0020;        // pin5 is enabled for peripheral function (TIMER7)
  W[P0]=R0.L;

  P0.L=LO(PORTG_MUX); // 0xFFC0 3214, 00= 1st peripheral function
  P0.H=HI(PORTG_MUX); // 01= 1st alternate peripheral function
  R0.L=0x0040;        // 10= 2nd alternate peripheral function
  W[P0]=R0.L;         // set bit7&6=01 for TMR7

// Bit1&0=01 Select Modes of Operation: PWM_OUT mode
// Bit2=1, PULSE_HI (0=Negative action pulse)(1=Positive action pulse)
// Bit3=1, PERIOD_CNT (1=Continuous pulses) (0=Single Pulse)
// Bit4=0, IRQ_ENA (1=interrupt request enable)
// Bit5=0, TIN_SEL (Timer Input Select) (1=TACLK)(0=TMRCLK)
// Bit6=0, OUT_DIS (1:no output/0:output on TMR pad in PWM_OUT mode)
// Bit7=0, CLK_SEL (1=PWM_CLK to clock counter) (0=SCLK)
//                  (PWM_CLK can be TACLK or TMRCLK)(TIN_SEL defines it)
// Bit8=0, TOGGLE_HI
// Bit9=0, EMU_RUN (1=Timer counter runs during emulation)
// Bit15&14=00, ERR_TYP
// 0x0000 0000 0000 1101 = 0x000D
P0.L = LO(TIMER7_CONFIG);   // 0xFFC0 0670
P0.H = HI(TIMER7_CONFIG);
R0.L = 0x000D;  
W[P0] = R0.L;  

// Set TIMER7_PERIOD
P0.L = LO(TIMER7_PERIOD);   // 0xFFC0 0678
P0.H = HI(TIMER7_PERIOD);
R0.L = 0x04E2;   // TIMER7_COUNTER=TIMER7_PERIOD then generate intr.
R0.H = 0x0000;   // Fsclk=25MHz (0.04us) then for 50us/0.04us=1250 (=0x04E2)
[P0] = R0;

// Set TIMER7_WIDTH
P0.L = LO(TIMER7_WIDTH);   // 0xFFC0 067C
P0.H = HI(TIMER7_WIDTH);
R0.L = 0x000A;   // TIMER7_COUNTER=TIMER7_WIDTH then generate intr.
R0.H = 0x0000;   // (0x0064)=100*0.04us=4us
[P0] = R0;

// Enable TIMER7 interrupt.
// Bit0=TIMER0, Bit1=TIMER1, Bit2=TIMER2, ..., Bit7=TIMER7
// SIC_IMASK1=0xbbbb bbbb bbbb bbbb bbbb bbbb tttt tttt
P1.L = LO(SIC_IMASK1);  // 0xFFC0 014C
P1.H = HI(SIC_IMASK1);
R0 = [P1];
BITSET(R0, 7); // Bit7=1
[P1] = R0;


// initiate TIMER7 Interrupt
// Default SIC_IAR4=0x5555 55555 (0xFFC0 0150)
// 5 means IVG12 (EVT12) interrupt priority
P1.L = LO(IMASK);  // IMASK 0xFFE0 2104: Interrupt Controller
P1.H = HI(IMASK);
R0.L = LO(timer7_isr);
R0.H = HI(timer7_isr);
[P1 + EVT12 - IMASK] = R0; // EVT12(0xFFE0 2030) ün içine timer7_isr in adresini yaz
R0 = [P1];
BITSET(R0, 12); // Enable TIMER7 interrupt
[P1] = R0;
// END: TIMER7 setup and interrupt
//////////////////////////////////////////////////////////////////////////////


//////////////////////////////////////////////////////////////////////////////
// Enable DMA4
P0.L = LO(DMA4_CONFIG); // 0xFFC0 0D08
P0.H = HI(DMA4_CONFIG);
R1 = W[P0] (Z);  
BITSET(R1,0);  // Set Bit0=1 for DMA4 Enable
W[P0] = R1;

// Enable ACM
P0.L = LO(ACM_CTL);  // 0xFFC0 3100
P0.H = HI(ACM_CTL);
R1 = W[P0] (Z);  
BITSET(R1,0);  // Set Bit0=1 for ACM Enable
W[P0] = R1;

// Enable SPORT1 RX to start a transfer
P0.L = LO(SPORT1_RCR1); // 0xFFC0 0920
P0.H = HI(SPORT1_RCR1);
R1 = W[P0];
BITSET(R1,0);  // Set Bit0=1 for SPORT1 Enable
W[P0] = R1;

// Enable TIMER7 counting
// TIMER_ENABLE=0xnnnn nnnn bbbb bbbb
// Bit0=Timer0_Enable, Bit1=Timer1_Enable, ..., Bit7=Timer7_Enable
// 0xnnnn nnnn bbbb bbbb
P0.L = LO(TIMER_ENABLE);   // 0xFFC0 0680
P0.H = HI(TIMER_ENABLE);
R0.L = 0x0080;   // TIMER7_ENABLE Bit7=1
W[P0] = R0.L;
ssync;
//////////////////////////////////////////////////////////////////////////////

  R0=0;
  R1=0;
  R2=0;
  R3=0;
  R4=0;
  R5=0;
  R6=0;
  R7=0;

_main.forever:

nop;         

jump _main.forever;
_main.end:

//////////////////////////////////////////////////////////////////////////////
// START: ACM INTERRUPT SERVICE ROUTINE
ACM_isr:
  [--SP] = RETI; // nesting of interrupts
  // clear ACM interrupt request
  P1.L = LO(ACM_ES); // 0xFFC0 3110
  P1.H = HI(ACM_ES);
  R1 = W[P1];
  BITSET(R1,5);  // W1C Bit5=1
  W[P1] = R1;

  // inset your code here
  R4 += 1;
  P0.L=LO(PORTFIO_TOGGLE); // 0xFFC0 070C
  P0.H=HI(PORTFIO_TOGGLE);
  R0.L=0x0004;       // W-1-to-toggle: LED2=0x0001, LED3=0x0002, LED4=0x0004
  W[P0]=R0.L;


  RETI = [SP++];
  rti;
ACM_isr.end:
// END: ACM INTERRUPT SERVICE ROUTINE 
//////////////////////////////////////////////////////////////////////////////

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