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AD7606 - Is a Convst allowed DURING read-out in serial-mode

Question asked by M.P on Jan 14, 2012
Latest reply on Jan 19, 2012 by clairec

Hello everyone,


I connected an AD7606 to a FPGA, working with Vdrive = 3,3 V and AD7606_CLK = 15 MHz. According to the Datacheet, the full throughput rate can be achieved when reading during conversion and using 5 V / 20 MHz. As far as I understand it, the 20 MHz are neede to finish the reading between convst and the following busy-low. Now, I was wondering what happens when I do the convst after I started reading the data, with a short delay. So, I am able to read the data with just 15 MHz and still finish reading before the busy-low flag and achieve the full throughput rate at 15 MHz.


Does this in any way decrease the conversion quality or disturb the functionality and accuracy?


I attached a copy of the FPGA signals, the relevant ones are marked. Please note, that the RESET signal is NOT the AD7606 reset!


Kind regards,