i am using AD9912 as Local oscillator,i have operated it in two mode
a) pll bypass mode(1GHz clk from sig gen)
b) pll enable mul=40(25 mhz clk from sig gen).
NB SFDR difference b/w two case is about 20dB means in case a NBSFDR is 20 dB more.
is it right or wrong.
what is phase noise specs for 25 MHz clk with multipliyer value=40