Ive picked up a 'working' design, that 'just' needs some tweaks,
Its an AD80066, running ALMOST as per fig 4 of the data sheet,
so its sha, but they are driving it as two channels , not two,
i.e. there are 2 adc clocks per cds, not four as per the diagram.
we are debating as to when does data come out of the chip in this case ?