it is possible to setup AD9371 no-OS successfully without adding a 30.72Mhz reference clk ??
Moved to No-OS subforum.
This was also discussed here: AD9371 No OS code without 30.72MHz reference
It will work, but please note that without the 30.720 MHz reference frequency applied to the REF_CLK_IN SMA connector, the PLL1 will not lock.
Thank you so much I will try
The AD9528 JESD204B Clock Generator has a loss of reference detection circuit. PLL1 Holdover is described as follows: In the absence of both input references, the device enters holdover mode. When the device switches to holdover mode, the charge pump tristates, allowing VCXO_VT to maintain its existing value for a period of time. Optionally, the charge pump can be programmed to force VCXO_VT to VDD/2. The device continues operating in this mode until a reference signal becomes available. If Automatic Holdover is enabled (0x010A) and the mode set to Vdd/2 (0x107) the VCXO's tuning line would be held constant. Although not phase locked to a master clock the reference drift would be held to a minimum.
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