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AD9361 PLL/CP Calibration time-outs

Question asked by andrei.tunea on Aug 9, 2018
Latest reply on Aug 10, 2018 by larsc

Dear community,

 

I have the following problem: I designed a board with a Xilinx Artix7 50T CSG325 FPGA and the AD9361. I tried to preserve the FMCOMSS3 design as much as possible. An important difference is that on my board the clock is fed to the AD9361 by an FPGA single ended LVCMOS25 pin. That pin is the output of a ODDR, that toggles between 1 and 0 with 40 MHz.

To reduce the 2.5 V amplitude and remove the offset of the clock going from the FPGA to the AD9361 I use a resistive divider 100R-100R and a 100n capacitor.

 

During the bring-up yesterday I came across the following problem: in total I have two boards, one can't calibrate the charge pump --> Calibration TIMEOUT (0x244, 0x80), the other can't calibrate the RX-, TX- and BB-PLL Calibration TIMEOUT (0x247, 0x2), Calibration TIMEOUT (0x287, 0x2) and Calibration TIMEOUT (0x05E, 0x8). I attached the UART output when the software runs in debug mode.

 

 

I looked at my clock signal on the oscilloscope before feeding it into the AD9361 and the amplitude and edges looked good. I also tried a capacitive voltage divider as discussed in this thread.

After connecting the 100n cap to the XTALN pin I measured the clock signal at the XTALN pin and noticed it wasn't DC free anymore. I'm not sure if it's the measurement itself that leads to the addition of DC to my clock signal, or the XTALN pin.

What I also tried: I fed 40 MHz from a clock generator (laboratory equipment) to the XTALN pin through 100n, amplitude 1.3V single ended square signal.

With all three types of clocks (resistive divided, capacitive divided, lab equipment) I got the same pll/cp calibration problems.

 

About the firmware: I started with the fmcomms2_kc705 fpga design and made the following modifications:

* removed MIG --> added an MMGM that generates 100 MHz and 200 MHz

* removed ADI DMA blocks

* removed IIC

* removed GPIO LCD

* removed ETHERNET (MDIO MII signals)

* removed linear flash

 

In the software I made the following modifications:

* removed read/write dma functions

* the linker script uses only the LMB BRAM resources (256 kB)

* Changed the parameter xo_disable_use_ext_refclk_enable to 1 in the default_init_param

 

I attached the complete UART output of the two boards and the default_init_param.

 

I am also willing to share the schematics and layout of my board, as well as FPGA design and software but not publicly.

 

With best regards,

Andrei

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