Our customer has an issue about output signal of LTC2312-12. Could you please support me?
The customer has used LTC2312-12 in their products. The output signal of TC2312-12 is fixed to Hi level or low level approximately one out of dozens of times when power ON/OFF.
Could you please refer following picture? SDO is fixed high level.
Could you please refer following picture? This is normal case. We can get the data normally from SDO pin.
We thought LTC2312-12 is in NAP mode. Then we send a pulse on the SCK. That timing is between the end of FPGA initial condition and first Hi signal on the CONV. But the issue was not improved.
And then, we added a pull-down resister to CONV pin. In this case, the CONV in the term of FPGA initial condition is low level. And in this case, the issue doesn't reproduce.
Do you have any ideas about the cause of this issue?