1.Appliction Background:The customer applies a 13-level cascade, and each single product is composed of 1 ADV7612+2 ADV7511 and STM32F4+ FPGA. STM32F429 is mainly used to configure the registers of ADV chip and EDIDetc., and FPGA is mainly used for image algorithm processing. The FPGA's processed vedio/image data sent to ADV7511, where one of ADV7511 is used for Loop output to preview the image of the current level and the other one been used for next level ADV7612's input of the cascade. The whole system mainly realizes the multi-screen splicing LED display. The input image resolution of the device support 1024*768 1320*768/1280*1024/1920*1080/1440*900/2560*960/1600*1200/1920*1200 @60hz.
2.Application issue:The output of the last level of the 13-level cascade in the DVI mode is consistent with the resolution of the original input signal, and no resolution anomaly occurs. However, in HDMI mode, the resolution of ADV7612 input signal will be abnormal after level 4, and it will continue until the last level (for example, input 1024* 768@60HZ, the resolution identified by ADV7612 at level 4 is 520*768@60, and even the resolution identified by level 8 and 9 is 256* 768@60hz). We think that the defference between HMDI mode and DVI mode mainly in the CSC, so we closed the ADV7612's CSC in HDMI mode. But there's noting changed. So, is there any other advice in this application?
The application block diagram shows below: