I'm reading the datasheet for long and I cannot find how the samples are mapped into frames, depending on the JESD mode.
Did I miss it?
Thanks in advance
It is done according to the JESD204 standard . The datasheet has some examples starting on page 76.
For an FPGA implementation you can use our generic ADC deframer module. See hdl/ad_ip_jesd204_tpl_adc_deframer.v at dev_ad9694 · analogdevicesinc/hdl · GitHub
It generates the right mapping based on the specified number of lanes and converters.
I didn't know there was a standard, thanks!
I will check the hdl design for more information.
Thank you larsc for responding.
LCr, please see examples 1 and 2 on pages 76 and 77 of the Rev0 datasheet. it shows the data framing for two use cases. Others can be derived from the standard as well. You can also get more generic information at www.analog.com/jesd204b
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