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Question asked by GiantSDR on Aug 7, 2018
Latest reply on Aug 8, 2018 by DougI

I'm using HSC-ADC-EVALC with AD9637-80EBZ sampling signal in 8 channels synchronously. And the memory in Virtex4 is not enough for my application, so i added 2 samsung ddr2 sram chips which's model name is K7i163682b.

But in my processing adding mig ip core into the ise project (Low_Speed_Octal_synchronous_capture), i found the mig core interface does not match with the FPGA to SRAM DATA part in schematic of HSC-ADC-EVALC.

for example, in mig interface list ,the K,K_n,C,C_n are all 2bits width,which in schematic are all 1bit , and cq_delay  in mig are only 2bits width, which in schematic shown an CQA,CQA_n,CQB_CQB_n.

MIG version: MIG3.61 in  ISE14.7 .

How Should i solve the problem ?