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Sending and receiving signals with IP axi_ad9361_v1_0 (AD9361/FMCOMMS3-EBZ)

Question asked by luatdh on Aug 6, 2018
Latest reply on Aug 12, 2018 by luatdh

Hello,

 

I'm using fmcomms2_zed reference project for Zedboard and FMCOMMS3-EBZ.

 

I'm making a design for radar application. So I want to send/receive signals directly to/from axi_ad9361_v1_0 (as you see in the 1st picture). I'm little confused here, As I saw in the block design, there's one clock signal (green highlighted wire) comes with input data bus (red one) and output data bus (blue wire). Here's what I have in mind, I'll make a custom HDL IP block with System Generator with Xilinx library and add it to the block design. The IP's sending DAC data signal (with as-high-as-possible clock sample rate) and receive ADC data (with 40MHz clock sample rate). That means I'll build a multi-clock system, send and receive data directly to the axi_ad9361_v1_0 IP block. But I have no idea which clock to use and how to use the IP block without any design document attached.

 

Can you help me find a solution for making the system?

 

Thanks a lot, guys.

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