We were doing a project which used 5 ADI AD9250BCPZ-250 on our custom board. The Main controller is XC7Z100-2ffg900I.
First,thanks to ADI engineer,we ported the fmcadc4 to our custom board. we also use AD9528 to realize 5 AD9250 clocks ,FPGA reference clock and sysrefs clocks. But we found the ADI open source Jesd204b rx can only support 8 lanes.
of cource, one AD9250 use two lanes,so we realized four AD9250,eight channels ADC syncronization. But our project will support 10 channels ADC syncronization.
We instance two adi-jesd204-rx open source IP,one for 8 lanes,another for two lanes. and we get the ten channels ADC input waveforms, we found the extra 2 lanes do not always had the certain phase relationship with the 8 channels when zynq is booted(Sometimes 8ns,Sometimes 0ns with other 8 channels).The two channels can not have fixed phase at zynq is booted.
Does anyone can help us. How to sync the two instance IP,and how to realize more than 8 lanes jesd204b-Rx syncronization.