Data sheet states
[All pins are three-stated during and immediately after reset,with the exception of EXTCLK, which toggles at the system clock rate.
Adding a parallel termination to EXTCLK may prove useful in further enhancing signal integrity. Be sure to verify overshoot/ undershoot and signal integrity specifications on actual hardware.]
But on checking the manual VR_CTL registers Reset Values is 0x 3000 which is EXTCLK_OE is cleared and manual also state
[When EXTCLK_OE is cleared, the EXTCLK pin is three-stated]
Which is correct is it Three stated or is it Toggling at SYSTEM CLOCK RATE(SCLK ) on and after RESET .
And what is correct termination if the function is not used as Data sheet and manual is confusing .