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FMCADC3, ZC706 & Xilinx JESD204 IP Core

Question asked by balabes@yahoo.com on Aug 3, 2018
Latest reply on Aug 3, 2018 by larsc

Hi! 

I want to use  AD-FMCADC3-EBZ in Subclass 0 and ZC706, but I have as ref_clk 625 MHz (ref_clk = Sample_Clock / 4= 2500 MHz / 4 = 625 MHz). In Xilinx JESD204 IP core I can't use 625 MHz as core_clock , if ref_clk = 625 MHz, I need global clock = lane rate / 40 = 156.25, but if ref_clk = lane rate/40 ref_clk is enough. How I can divide ref_clk by 4, to use it as core clock in Xilinx JESD204 IP?

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