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AXI SPI Engine

Question asked by mxdsgnl on Aug 2, 2018
Latest reply on Aug 7, 2018 by mxdsgnl

Hi I am trying to use the AXI SPI Engine IP with DATA_WIDTH=21.

 

I'm not sure how to properly load the data_fifo so that all transfers are 21 bits long. 

 

I also see that when I crank up the frequency, the delay between CS and the first clock edge is ~1.8µs regardless of the CS assert setting.

 

Thanks,

Nick

 

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After reviewing the HDL I see that there is a requirement to set DATA_WIDTH to 8/16/24/32.

 

I am still running into an issue where the first word matches the DATA_WIDTH but all subsequent word transfers are 32bits.

 

Thanks,

Nick

 

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After further review of the HDL it is apparent that DATA_WIDTH should be 8/16/32, not 24.  Reason for this is that transfer count is only incremented after the counter counts past bit_counter.  In the case of DATA_WIDTH = 24, bit counter is still 5 bits wide and transfer count will only increment after 32 (2^5) and not 24 = 0'b11000.

 

Sure would be nice if transfer counter incremented when bit counter was equivalent to DATA_WIDTH.

 

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Okay - I can pack my spi message using the Uint8_t type so the DATA_WIDTH is not a problem.

 

I would like to be able to control the time between CSn asserted and the transfer activation.  This seems to be 1.8us no matter what I do.  There is no sleep command being compiled, nothing that I see that causes this initial delay.  I will keep looking but would appreciate any advice to move past this.

 

Thanks,

Nick

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