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Port AD9371 reference design to custom board

Question asked by ebray on Aug 1, 2018
Latest reply on Aug 2, 2018 by AdrianC

We have designed a custom board that utilizes a XCKU085 and an AD9371. I have successfully built the reference design for the KCU105 board which hosts an XCKU040 part. I assumed it would be a fairly straightforward migration using your porting guide:

 

Porting ADI's HDL reference designs [Analog Devices Wiki] 

 

Unfortunately, I wasn't having much success so I decided to slowly iterate through the porting process. I copied the board and project files for the KCU105 to new "hub" folders. Then I changed all of the "kcu105" references in the tcl files to "hub". I also added the project to adi_project.tcl like this:

 

  if [regexp "_hub$" $project_name] {
    set p_device "xcku040-ffva1156-2-e"
    set p_board "xilinx.com:kcu105:part0:1.1"
    set sys_zynq 0
  }

 

When I run make with this setup the build completes successfully. This builds a project identical to the kcu105 one. My next step was to remove the board reference in adi_project.tcl since I don't have development board files. I saw a couple other projects used "not-applicable" and so I did the same:

 

set p_board "not-applicable"

 

When I ran make after that I received some errors for the DDR4 controller:

 

### ad_ip_instance ip:ddr4 axi_ddr_cntrl
create_bd_cell: Time (s): cpu = 00:00:08 ; elapsed = 00:00:09 . Memory (MB): peak = 982.027 ; gain = 121.703
### ad_ip_parameter axi_ddr_cntrl CONFIG.C0_CLOCK_BOARD_INTERFACE default_sysclk_300
ERROR: [IP_Flow 19-3461] Value 'default_sysclk_300' is out of the range for parameter 'C0 CLOCK BOARD INTERFACE(C0_CLOCK_BOARD_INTERFACE)' for BD Cell 'axi_ddr_cntrl' . Valid values are - Custom
INFO: [IP_Flow 19-3438] Customization errors found on 'axi_ddr_cntrl'. Restoring to previous valid configuration.
ERROR: [BD 41-245] set_property error - Value 'default_sysclk_300' is out of the range for parameter 'C0 CLOCK BOARD INTERFACE(C0_CLOCK_BOARD_INTERFACE)' for BD Cell 'axi_ddr_cntrl' . Valid values are - Custom
Customization errors found on 'axi_ddr_cntrl'. Restoring to previous valid configuration.

 

ERROR: [Common 17-39] 'set_property' failed due to earlier errors.

 

    while executing
"rdi::set_property CONFIG.C0_CLOCK_BOARD_INTERFACE default_sysclk_300 /axi_ddr_cntrl"
    invoked from within
"set_property ${i_param} ${i_value} [get_bd_cells ${i_name}]"
    (procedure "ad_ip_parameter" line 3)
    invoked from within
"ad_ip_parameter axi_ddr_cntrl CONFIG.C0_CLOCK_BOARD_INTERFACE default_sysclk_300"
    (file "E:/adi/hdl/projects/common/hub/hub_system_bd.tcl" line 85)

 

    while executing
"source $ad_hdl_dir/projects/common/hub/hub_system_bd.tcl"
    (file "system_bd.tcl" line 7)

 

    while executing
"source system_bd.tcl"
    (procedure "adi_project_xilinx" line 104)
    invoked from within
"adi_project_xilinx adrv9371x_hub"
    (file "system_project.tcl" line 6)
INFO: [Common 17-206] Exiting Vivado at Wed Aug  1 21:31:41 2018...

 

These seem to be related to the fact that some of these signals were defined in the KCU105 development board files. I changed three lines in my hub_system_bd.tcl file to use a value of "Custom":

 

ad_ip_parameter axi_ddr_cntrl CONFIG.C0_CLOCK_BOARD_INTERFACE Custom
ad_ip_parameter axi_ddr_cntrl CONFIG.C0_DDR4_BOARD_INTERFACE Custom
ad_ip_parameter axi_ddr_cntrl CONFIG.RESET_BOARD_INTERFACE Custom

 

Then I get this error:

 

connect_bd_net -net /sys_mem_clk /axi_ddr_cntrl/c0_ddr4_ui_clk
### ad_connect  sys_mem_clk axi_ddr_cntrl_rstgen/slowest_sync_clk
connect_bd_net -net /sys_mem_clk /axi_ddr_cntrl_rstgen/slowest_sync_clk
### ad_connect  sys_cpu_clk axi_ddr_cntrl/addn_ui_clkout1
ERROR: [Common 17-55] 'get_property' expects at least one object.
Resolution: If [get_<value>] was used to populate the object, check to make sure this command returns at least one valid object.

 

    while executing
"source $ad_hdl_dir/projects/common/hub/hub_system_bd.tcl"
    (file "system_bd.tcl" line 7)

 

    while executing
"source system_bd.tcl"
    (procedure "adi_project_xilinx" line 104)
    invoked from within
"adi_project_xilinx adrv9371x_hub"
    (file "system_project.tcl" line 6)
INFO: [Common 17-206] Exiting Vivado at Wed Aug  1 21:47:10 2018...

 

I have also tried removing the three offending lines but I receive the same error. Can you please provide guidance on how to resolve this issue?

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