I designed a 0.9V 36A power circuit for my FPGA using LTM4630. The design refered to the circuit given in Figure 24 of the datasheet. The detail is given in the following figure.
where C115 is 2.2uf instead, and the voltage of INTVcc is normally 5V. The output FPGA_0V9D2 has three 220uF SMD aluminum electrolytic capacitors and several 0.01uF-22uF ceramic capacitors for filtering the output ripple. Vaux_5V is obtained by another switching circuit and works well. Vin is 7V when powered up.
The problem is that after powered up, when the output voltage reaches 0.9V, the output becomes unstable. At this time, because the voltage is unstable increased, the output current is too large, and both the load and LTM4630 are hot. After about a few seconds of work, my power supply enters the current limit protection. After the protection is removed, the phenomenon remains unchanged. If the output is disconnected and 0.9V is supplied from an external power supply, the current at 0.9V is about 1A, and the FPGA can be detected by JTAG. When I generate the 0.9V core power by the LTM4630 , the output current of the LTM4630 exceeds 10A. The peak voltage of the unstable output is about 2V which exceeds the maximum allowable by the FPGA, but the FPGA is still not damaged. The unstable 0.9V output is shown below.
The output with 20M bandwidth is shown in the following figure.
The fset voltage was connected to the INTVcc to change the switching frequency when debuging, but the phenomenon remains unchanged. At present, it is suspected that there is a problem with the connection of COMP, but I think it may have other problems in the design.
Sorry for my bad English.