I am using the AD9371. I need +-0.1 ppm frequency stability so I am using an OCXO as the reference clock. With this "clean" reference, I don't see the point of using the AD9528 as in the reference design. My plan was to split the OCXO signal (100 MHz) to the AD9361 DEV_CLK pins and to the AD9528. I would use the AD9528 to produce the clocks for JESD204B and other FPGA clocks. The frequency stability of the overall system will be driven by the OCXO. The phase noise of the OCXO is much better than phase noise of any VCXO that will used in the PLL of the AD9528.
Is there a reason I should send the OCXO signal through the AD9528 in order to create the clock for the AD9371?