We created our own design with two AD9361s on a single board for a total of four synchronized RX channels. Everything seems to be in order with the exception of the noise floor in our received signal - see attached. On the left is the I/Q time-domain plot receiving a PN sequence, while the right is the power spectrum. We're not quite sure why the noise floor is so high, since a previous trial with the FMCOMMS5 board with the same configuration resulted in significantly less noise (by about an order of magnitude).
We're using the AD9361 driver provided on Github. Some hopefully relevant information regarding the RX signal chain for both chips:
-All four input RF paths are unbalanced
-RX path frequencies: 983040000, 245760000, 122880000, 61440000, 61440000, 61440000
-AGC is disabled (manual control enabled)
-digital gain is disabled
-ad9361_set_rx_rf_gain() is called with a value of 5
At this point, we've run out of ideas. Any help would be greatly appreciated.