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Configuring the AD9957 for single tone using the VIRTEX 6 FPGA

Question asked by Tronic on Jan 9, 2012
Latest reply on Feb 22, 2012 by DSB



I've been trying for a while now to run the AD9957 in single tone to generate a 240 MHz sine output using the FPGA. I'm using the onboard 25 MHz oscillator and an SCLK of 5MHz. I've configured the CFR1 register as x01410002 -- single tone, The CFR2 register is set to x00400000 and the CFR3 reg is set to x153F0150 [VCO5 select and 40 multiplying factor] and I chose profile 0 and input 3D70A3D7 for 240 MHz. My program selects the PS<2:0> = 000 CSB = 0  IO_RESET = 0  and on every rising edge I asert  first the registrer to be writen too and then the contents of the registers. At the begining of my program I set the Master resert to 1 and after one period I set it to zero. At the end of the program I set IO_UPDATE to one and I clear it at the begining of the  program. The problem I have is the I'm not getting any output and the Master reset and Ext_PWR_DWN on the board are always high. 'M I missing something?