Question asked by peteluds on Jul 30, 2018

I’m looking to generate a 19.0685-19.1815 GHz chirped signal with 32.77 uS chirp time for an FMCW radar application; for generation of highly linear chirped signals for FMCW radar systems it is often recommended that a DDS is used as they can use very small frequency steps in generating the ramp.

I’m planning to use the AD9956 DDS to generate a chirped signal with 100 MHz centre frequency and then use this as a reference signal for a TI LMX2492 PLL / Macom MAOC-009265 VCO. Delta Frequency Tuning Word (DFTW) and system clock (SYSCLK) limitations of the AD9956 mean that:

• Minimum Delta frequency step size = DFTW * SYSCLK / (2^24) = 1*400e6/(2^24) = 23.84 Hz
• Minimum time step = 1/(SYSCLK/4) = 1/(400e6/4) = 10 nS

The closest I can get to above 19.0685-19.1815 GHz chirped signal with 32.77 uS chirp time is to use:

• Delta frequency step size = 190.72 Hz (DFTW = 8)
• Time step = 10 nS
• Number of steps = 3277
• PLL divider ratio = 95.625

This generates a 19.0652-19.1848 GHz chirped signal. I intend to measure the linearity of this signal at the end of August but I was wondering if there is any way to simulate or calculate the likely linearity? The frequency step size at the VCO will be = 190.72*95.625*2 = 36.475 KHz. I’m intending to use a loop filter bandwidth of 440 KHz or greater so I guess this should be ok in terms of maintaining lock at the PLL.

How would the linearity of the Fractional-N PLL chirp generation technique using the ADF4159 and fixed TCXO reference compare (TI LMX2492 also has this feature)?

I guess that for the ADF4159:

• Minimum frequency step size (assuming 100 MHz PFD frequency) = fPFD/(2^25) = 100e6/(2^25) = 2.98 Hz.
• Minimum time step (assuming 100 MHz PFD frequency) = CLK1 * CLK2 * (1/fPFD) = 1 * 2 * (1/100e6) = 20 nS

Therefore, could use following settings to give 19.0685-19.1815 GHz chirped signal with ADF4159 and fixed TCXO reference:

• Frequency step at VCO = 68.94 KHz
• Number of steps = 1639

As far as I can tell it is the minimum time step that is the limiting factor in the achievable linearity in these cases, would that be correct? i.e. with the AD9910 for instance, which allows SYSCLK of up to 1 GHz, could have minimum time step of 1/(SYSCLK/4) = 1/(1e9/4) = 4 nS.

Are there any other advantages to using a DDS to generate chirped signal rather than the Fractional-N PLL technique?