AnsweredAssumed Answered

failure to sync on AD9957

Question asked by timothy.starr on Jan 9, 2012
Latest reply on Feb 22, 2012 by DSB

We are having problems with AD9957 multi-chip synchronization.

 

AD9957 REF_CLK is provided with 20MHz clock input, SYNC_IN is provided with 100KHz clock input. SYSCLK is set at 1GHz. The PLL is locked, but we see the Synchronization Sample Error (SNC_SMP_ERR high). Adjusting input delay takes no effect

 

The AD9957 register setting is:

 

CFR1: 0x 00400002

CFR2: 0x 00402800

CFR3: 0x 0518C164

Multichip Sync: 0x 08000000

 

We have tried to lower the SYSCLK to 400MHz, and adjust the input delay, the synchronization seems to work. The following is the register set up:

 

CFR1: 0x 00400002

CFR2: 0x 00402800

CFR3: 0x 0018C128

Multichip Sync: 0x 08000020

 

We need to run at 1GHz sysclk, though.

 

Could you take a look at it?

Is there atiming requirement for the sync input set up and hold requirement with regard to the SYSCLK?.

 

Thank you. And best regards

 

Tim Starr on behalf of JW@AC.

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