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hdl project dev_ad9172_fmc - continuous or burst-mode only?

Question asked by jjxia on Jul 27, 2018
Latest reply on Jul 30, 2018 by jjxia



I have built AD9172 FMC under dev_ad9172_fmc branch. 


In the block design, the ulti_dacfifo input data (from DMA, 256 bit wide) is clocked at 100 MHz (from Zynq PL0). The fifo output data to DAC core is played at > 300 MHz clock rate at 256 bit wide. 


Does this mean the DAC only allows bursts of output, instead of continuously playing back the content of memory?


Thank you