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libIIO FIFO backend?

Question asked by oclabbao on Jul 24, 2018
Latest reply on Jul 26, 2018 by oclabbao

Good day!

 

This is both a question on feasibility and (perhaps) a feature request. If this is not feasible, please feel free to shoot it down.

 

For the ADRV936x modules and its associated carrier boards, I found the USB2 interface a bit limiting. I was toying with the idea of upgrading to USB3.0 by using USB3-to-FIFO bridge chips. One possible combination would be ADRV9364 SOM + FMC Carrier board + UMFT60xx which uses FTDI FT60x chips. Hardware-wise, this combo seems feasible (or is it?), with some additional blocks on the Zynq PL.

 

The more critical concern would be how libIIO should communicate with the FIFO bridge on both ends. From the target side, the kernel won't see this as USB but as a FIFO memory. From the host side, it may recognize this as USB, but maybe not a libIIO USB backend.  

 

So is this even feasible? If yes, what needs to be done on libIIO or kernel drivers for this to work? I'm thinking something like the libIIO UART backend, but instead of UART, we have a FIFO to USB3.

 

Thanks for any enlightenment on the matter!

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