Hello,I am trying to interface a custom IP to "axi_ad9371_core" in the ADRV9371 reference design. I think the signals of interest are:
My understanding is that the default sample rate is 245.76 MSPS (that is what I see in Lunux GIU). The 32 bit dac_data
buses are carrying two 14-bit samples on every dac_clk, which is therefore should be 122.88MHz (half the sample rate).
However, bringing out dac_clk to the external GPIO pin and measuring its frequency shows the measured frequency of dac_clk being 61.44 MHz, which contradicts my understanding.
What is the relationship between sample rate of the DAC, dac_clk signal, and data on dac_data buses?