AnsweredAssumed Answered

What is rate of dac_clk signal  in axi_ad9371_core of reference design hdl-hdl_2018_r1 for AD9371 board?

Question asked by DSPdesigner on Jul 24, 2018
Latest reply on Jul 25, 2018 by lnagy

Hello,I am trying to interface a custom IP to "axi_ad9371_core" in the ADRV9371 reference design. I think the signals of interest are:

 

TX1:

dac_data_i0[31:0]    

dac_data_q0[31:0]

TX2:

dac_data_i1[31:0]

dac_data_q1[31:0]

Clock:

dac_clk

 

My understanding is that the default sample rate is 245.76 MSPS (that is what I see in Lunux GIU). The 32 bit dac_data

buses are carrying two 14-bit samples on every dac_clk, which is therefore should be 122.88MHz (half the sample rate).

 

However, bringing out dac_clk to the external GPIO pin and measuring its frequency shows the measured frequency of dac_clk being 61.44 MHz, which contradicts my understanding. 

 

What is the relationship between sample rate of the DAC, dac_clk signal, and data on dac_data buses? 

 

Please clarify. 

 

Outcomes