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AD9172 with ADS7v2 subclass problem

Question asked by LCr on Jul 24, 2018
Latest reply on Jul 25, 2018 by landsman

Hello,

 

I'm working with AD9172-EBZ and ADS7v2.

I'm trying to generate a sine thanks to NCOs.

My config is the following :

  • JESD mode 2
  • data rate = 125 MHz
  • DAC clock = 3 GHz (PLL disabled)
  • Subclass 1.

I program it with ACE, then I load DC thanks to DPG downloader. It synchronized well and I even have desired outputs.

However, I realised that the subclass selected in DPG downloader is 0 instead of 1.

So I changed it and now there is no output anymore though all is still synchronized.

I first thought it was a bug in the software, but when I check the DAC registers, the received JESD parameters show that subclass used by the FPGA is correspond to the one of DPG downloader.

 

Could someone help me understand what is the problem?

 

Thanks in advance,

LCr

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